This invention relates to a CMOS inverter circuit and more particularly to a CMOS inverter including a compensation circuit which adjusts the inverter's input threshold to stabilize it over a range of V.sub.cc and temperature.
A conventional CMOS inverter 10 is shown in FIG. 1. Inverter 10 includes a pMOS transistor 12 and a nMOS transistor 14. A gate 12g of pMOS transistor is coupled to a gate 14g of nMOS transistor 14. A first flow electrode 12s of transistor 12 is coupled to V.sub.cc and a first flow electrode 14s of transistor 14 is coupled to ground. A second flow electrode 12d of transistor 12 is coupled to a second flow electrode 14d of transistor 14. The switching threshold of inverter 10 is dependent on the relative size of transistors 12 and 14 and the supply voltage V.sub.cc. The higher the ratio of pMOS to nMOS, the higher the input threshold. If we assume for a typical circuit that the input threshold is V.sub.cc /2 and that V.sub.cc is allowed to vary from 2.7 to 3.6 volts, the input threshold could then vary from 1.35 to 1.8 volts. This is undesirable, for example, if the input of inverter 10 is a clock pulse specified to ramp from 2.7 to 0 volts with a 2.5 ns slew rate and the design requires the propagation time of the clock signal to be independent of V.sub.cc.
In addition, changes in temperature can change the effective size of the transistors in the inverter which results in changes in the switching threshold.
Accordingly, it would be desirable to provide a CMOS inverter including circuitry which could maintain the switching threshold as V.sub.cc and temperature vary.
Also, because subsequent circuits may also vary with changes in V.sub.cc and temperature, it would be desirable to have an input threshold which changes in a compensating manner with V.sub.cc and temperature.